The present invention relates to a method and apparatus for a rail-to-rail amplifier. In particular, the present invention relates to a method and apparatus that uses a rail-to-rail amplifier with a reduced gain, allowing the compensation network to be reduced in size while maintaining suitable stability over the amplifiers operating voltage range.
Differential amplifiers normal only operate over a limited range of input voltages. The maximum input voltage range for which a circuit continues to operate as an amplifier is termed the input common-mode range (CMR). When the input voltages (or common mode voltage) exceed the input CMR, transistors become cutoff, saturated, or breakdown in one or more gain stages of the amplifier. Typically, the CMR permits the common mode voltage (VCM) to approach within a few volts of either power supply voltage before the amplifier performance is degraded.
A typical differential amplifier (100) is shown in FIG. 8. As shown in the figure, a current source IDIFF sources a current into node 1002. Transistor M1 has a source connected to node 1002, a gate connected to INN and a drain connected to node 1001. Transistor M2 has a source connected to node 1002, a gate connected to INP, and a drain connected to node 1003. Transistor M3 is a diode-connected transistor with a gate and drain connected to node 1001, and a source connected to VSS. Transistor M4 has a gate connected to node 1001, a drain connected to node 1003, and a source connected to VSS. Transistor M5 has a gate connected to node 1003, a drain connected to VOUT and a source connected to VSS. A second current source IOUT sources a current into the drain of transistor M5 (VOUT). A capacitor (CC) is connected between VOUT and node 103.
Transistors M1 and M2 are a matched pair of PMOS transistors that form a differential input stage of the differential amplifier (1000). Transistors M3 and M4 form an NMOS current mirror, acting as a load for the differential input pair (M1, M2). Current source IDIFF supplies a xe2x80x9ctail currentxe2x80x9d to bias the differential input pair transistors into their active region of operation. NMOS transistor M5 serves as an amplifier, with an input at node 1003 and an output at VOUT. A capacitor (CC) reduces the gain of the amplifier at high frequencies to provide a stable amplifier by Miller compensation.
The input differential pair transistors (M1, M2) limit the CMR of differential amplifier 1000. Transistors M1 and M2 must be biased in saturation for the amplifier to function properly. A typical threshold voltage of a PMOS transistor (VTP) is on the order of xe2x88x921V. To remain in saturation, the source-to-gate voltage (VSG) of transistors M1 and M2 must be biased active (VSGxe2x89xa7|VTP|). Since the input differential pair transistors will be cutoff when VCM (the DC level at INM and INP) approaches the VDD power supply, the input differential pair transistors will operate as an amplifier when: VG1 (max)=VG2 (max)=VCM (max)≅VDDxe2x88x92|VTP|. The active load transistors (M3, M4), together with the input differential pair transistors (M1, M2) determine the minimum VCM for which the amplifier will operate properly. Transistors M1 and M2 must also have a source-to-drain voltage (VSD) that exceeds the saturation voltage (VSDxe2x89xa7VSGxe2x88x92|VTP|). The typical threshold voltage of a NMOS transistor (VTN) is on the order of +1V. The load transistors M3, M4 must be biased active (VGS3=VGS4 greater than VTN). The minimum VCM for amplifier 1000, is determined by: VG1 (min) =VG2 (min)=VCM (min)≅VSS+VTNxe2x88x92|VTP|. Thus, amplifier 1000 does not operate as a rail-to-rail amplifier.
The unity-gain bandwidth (GBW) is defined as the frequency where the gain is 0 dB. Since CC creates a dominant pole in the amplifier, the unity gain bandwidth (GBW) is xcfx89≅gm/CC, where gm is the trans-conductance of the amplifier.
In accordance with the invention, the above and other problems are solved by an apparatus and method that reduces an overall gain in a rail-to-rail amplifier. The reduced overall gain permits employment of a reduced size compensation network in compensating the apparatus, and thereby reduces the xe2x80x9con-chipxe2x80x9d area used by the compensation network.
Briefly stated, the present invention relates to a rail-to-rail amplifier having a first and second input stage amplifier, and an output stage amplifier that provides rail-to-rail operation. The rail-to-rail amplifier is driven by an input signal with a particular common-mode voltage. The first amplifier is active during a first range of common-mode voltages, while the second amplifier is active during a second range. A monitor circuit includes an input differential pair that is sized to operate at the same common-mode voltages as the first input differential pair in the first amplifier. The monitor circuit senses when the first amplifier has reached a condition where the amplifier begins to stop working by monitoring a current flowing in the input differential pair. The monitor circuit controls the bias current in the second amplifier""s bias circuit such that the second amplifier is enabled when the current in the input differential pair drops down towards zero. The outputs of the first input stage amplifier and the second input stage amplifier are coupled to the input of the output stage amplifier. Since the first and second input stage amplifiers are not on at the same time, the overall gain in the amplifier is reduced. Reducing the gain of the rail-to-rail amplifier results in a reduced size of a compensation capacitor that is coupled across the input and output of the output stage amplifier. The reduction in gain and compensation capacitor results in a lowered amount of chip space and reduced cost for the rail-to-rail amplifier.
According to a feature of the invention, an apparatus for amplifying a signal includes a first and second input stage amplifier, and an input amplifier monitor circuit. The input amplifier monitor circuit senses an operating state of at least one of the input stage amplifiers to produce a control signal. The control signal is used to control one of the input stage amplifiers such that the overall gain of the apparatus is limited.
In one embodiment of the invention, the first input stage amplifier operates over a first range of common-mode voltages. The gain is limited by disabling the second amplifier when the first input stage amplifier is operating.
In another embodiment of the invention, the apparatus further includes a controller circuit. The controller circuit disables the second amplifier in response to the control signal when the common-mode voltage is in a first range. The controller circuit enables the second amplifier in response to the control signal when the common-mode voltage is in a second range.
In a further embodiment of the invention, the apparatus further includes a controlled bias circuit that has a bias output. The bias output is coupled to the second input stage amplifier. The controlled bias circuit selectively disables the second input stage amplifier by disabling the bias output in response to the control signal.
In another embodiment of the invention, the first input stage amplifier has a first differential input pair of transistors. The input amplifier monitor circuit includes a second differential input pair of transistors. The transistors of the first differential input pair and the second differential input pair are of a same type (e.g. PMOS). When the second differential input pair is operating at a common-mode voltage in a first range, the second input stage amplifier is disabled by the control signal. Also, the first differential input pair and the second differential input pair may share a common source connection.
In yet another embodiment of the invention, the first and second input stage amplifiers are trans-conductance amplifiers having first and second outputs respectively. The first and second outputs are coupled to a common node. Also, a compensation network may be coupled to the common node, such that the compensation network compensates the gain of the apparatus (e.g. limits the gain). The compensation network normally includes a capacitor. By limiting the gain of the apparatus, the size of the capacitor in the compensation network is also reduced.
In an embodiment of the invention, the input amplifier monitor circuit includes a current sense circuit and a differential pair of transistors. The current sense circuit produces a control signal that is responsive to current flowing in the differential pair of transistors.
Another embodiment of the invention includes a bias circuit that cooperates with an input amplifier monitor circuit. The bias circuit produces a bias voltage that is coupled to the second input stage amplifier. The bias voltage disables the second input stage amplifier when the first amplifier is operating. The bias circuit may further include a first current source, a second current source and a current sense circuit. The first current source generates a first current. The second current source is controlled by the control signal, and generates a second current. The current sense circuit senses a difference between the first current and the second current to produce the bias voltage.
In yet another embodiment of the invention, the input amplifier monitor circuit includes a current monitor circuit. The current monitor circuit monitors a sample current from at least one of the first input stage amplifier and the second input stage amplifier. The sample current is related to the control signal. The sample current changes as the input common-mode voltage approaches a power supply voltage. The control signal changes when the sample current changes such that the first input stage amplifier is gradually disabled and the second input stage amplifier is gradually enabled. By enabling and disabling the second input stage amplifier, the overall gain of the apparatus does not increase.
Another embodiment of the invention relates to a method for amplifying a signal. In operation, the method provides for gaining the signal with an amplifier and another amplifier to produce an output and another output respectively. The method also includes combining the output and the other output to produce another signal that is amplified to produce an amplified signal. By disabling the other amplifier when the signal is in a common-mode voltage range where the amplifier is operable, the overall gain from the signal to the amplified signal is reduced. By enabling the other amplifier when the signal is in another common-mode voltage range where the amplifier is inoperable, rail-to-rail operation is provided. Also, compensating the overall gain is achieved by coupling a compensation network between the other signal and the amplified signal. Furthermore, disabling the other amplifier may include sensing the condition of the amplifier to produce a control signal, and disabling a bias current in the other amplifier in response to the control signal. By disabling the bias current, the other amplifier is disabled.
According to yet another embodiment of the invention, an apparatus for amplifying a signal includes a first and second means for amplifying the signal, means for sampling a current in the first means for amplifying, means for disabling the second means for amplifying when the current is in a first range, and means for enabling the second means for amplifying when the current is in a second range. By enabling and disabling the second means for amplifying an overall gain in the apparatus is reduced. Also, the means for limiting the gain may include a means for compensating, the means for disabling the second means for amplifying, and the means for enabling the second means for amplifying.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.